As the continuous physical scaling is facing the increasing challenges in today’s CMOS technology, introduction of high mobility channel material has further increased its value as the device performance booster. SiGe is the leading candidate for p-channel device thanks to the high hole mobility. In order to benefit from the high intrinsic carrier mobility at a low VDD operation, low-Dit gate stack needs to be developped. However, the presence of GeO is known to increase Dit and degrade gate stack reliability. One of the effective passivation scheme for SiGe-based channel surface uses epitaxially-grown ultrathin Si. It suppresses the formation of GeO and enables to form high-k/SiO2 gate stack similar to that on Si devices. The outstanding improvement by using Si-cap was previously highlighted on pure Ge channel devices, where the formation of GeO is almost inevitable without the use of Si-cap. On the other hand, it poses some concerns such as EOT penalty and process controllability, making the Si-cap-free route as the most desired option as long as the interface and oxide bulk defect densities are kept under control. In this presentation, we will review our recent researches on Si-cap-free SiGe gate stacks, and discuss what the key is to the low-Dit SiGe gate stack.

Hiroaki Arimura received M.S. and Ph.D. in Engineering from Osaka University in 2009 and 2011, respectively. In 2011, he joined the reliability group of imec, Belgium, as a postdoc fellow of KU Leuven. In 2013, he joined logic technology department of imec as an R&D engineer, and started to be involved in Ge and later on SiGe gate stack research. He is currently working on group-IV gate stack module as a principal member of technical staff. He has been serving as a committee member of SSDM since 2017.